Three-dimensional wordline sharing memory
US9711209B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 16, 2016 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Mar 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.