Method for forming chip package
US9711403B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2012 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Jan 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15788
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least two conducting pads are disposed on the first surface of the substrate; partially removing the substrate from the second surface of the substrate to form at least two holes extending towards the first surface, wherein the holes correspondingly and respectively align with one of the conducting pads; after the holes are formed, partially removing the substrate from the second substrate to form at least a recess extending towards the first surface, wherein the recess overlaps with the holes; forming an insulating layer on a sidewall and a bottom of the trench and on sidewalls of the holes; and forming a conducting layer on the insulating layer, wherein the conducting layer electrically contacts with one of the conducting pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.