Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
US9711407B2 · kind B2 · utility
19Cited by
312References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 16, 2010 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Jul 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.