Multi-layer substrate with an embedded die
US9711459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2016 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Apr 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/2064
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a multi-layer substrate structure with an embedded die to miniaturize designs and improve performance. The multi-layer substrate structure includes a core layer having a cavity and a die mounted within the cavity. The die has a die body, a die conductive element on a top surface of the die body, and a dielectric layer over the die conductive element. The multi-layer substrate structure also includes a substrate conductive element formed over a portion of a top surface of the core layer and extending over at least a portion of the die conductive element. Overlapping portions of the die conductive element and the substrate conductive element are separated by the dielectric layer and form an electronic component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.