Package arrangement including external block comprising semiconductor material and electrically conductive plastic material

US9711462B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Gottfried Beer · Nittendorf, DE
• Dominic Maier · Pleystein, DE
• Ulrich Wachter · Regensburg, DE
• Daniel Kehrer · Eferding, AT

Key dates

• Filing date: May 8, 2013
• Grant date: Jul 18, 2017
• Expiry date: May 8, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/181
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In various embodiments, a package arrangement may be provided. The package arrangement may include at least one chip. The package arrangement may further include encapsulation material at least partially encapsulating the chip. The package arrangement may also include a redistribution structure over a first side of the chip. The package arrangement may further include a metal structure over a second side of the chip. The second side may be opposite the first side. The package arrangement may additionally include at least one of a semiconductor structure and an electrically conductive plastic material structure electrically coupled to the redistribution structure and the metal structure to form a current path between the redistribution structure and the metal structure.