Non-volatile memory having a gate-layered triple well structure
US9711516B2 · kind B2 · utility
1Cited by
19References
20Claims
0Family size
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Key dates
| Filing date | Oct 30, 2015 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Oct 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory structure includes a semiconductor substrate and a first layer of a first dopant type in the semiconductor substrate. The non-volatile memory structure further includes a first well region of a second dopant type over the first layer, a second well region of the second dopant type over the first layer and spaced apart from the first well region, and a third well region of the first dopant type disposed between the first well region and the second well region and extending downward to the first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.