Fine delay structure with programmable delay ranges
US9712144B2 · kind B2 · utility
2Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2015 |
| Grant date | Jul 18, 2017 |
| Priority date | — |
| Expiry date | Sep 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.