At-speed integrated circuit testing using through silicon in-circuit logic analysis
US9714978B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Apr 12, 2013 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Nov 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/311
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method, system, and computer program product for integrated circuit wafer and die testing. The method commences by selecting areas of interest accessible from a backside of an integrated circuit where the areas of interest correspond to electronic devices (e.g., gates or transistors or vias or pads). Then, using a small-beam light source such as a laser, illuminating the areas of interest and collecting the reflected signal returned from illuminated areas of interest. A processor analyses the reflected signal to determine logic states and timing information of the electronic devices and compares the determined logic states and timing information to a pre-determined logic pattern to identify one or more errors as observed from the actual electronic devices. Specific points within an area of interest are determined from CAD layout data, and the pre-determined logic patterns can be retrieved from CAD simulation data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.