Power reduction in a parallel data communications interface using clock resynchronization
US9715270B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2016 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Feb 10, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital data communications mechanism includes multiple parallel lines, in which components of one or more lines are temporarily powered down to save power. Preferably, both the transmitter and receiver contain respective generators generating identical pre-determined pseudo-random bit streams, which are initially synchronized and which remain powered up when the line is temporarily powered down. Upon re-powering the line, the transmitter transmits the locally generated bit stream, and the receiver compares the received bit stream with its internally generated bit stream to determine an amount of shift required for re-synchronization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.