Patent · US Active

Automatic built-in self test for memory arrays

US9715944B1 · kind B1 · utility

0Cited by

5References

4Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Lior Binyamini · Nes Ziona, IL
Stefan Payer · Stuttgart, DE
Wolfgang Penth · Holzgerlingen, DE
Ido Rozenberg · Nesher, IL

Key dates

Filing date	Jun 15, 2016
Grant date	Jul 25, 2017
Priority date	—
Expiry date	Jun 15, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/4402
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory array includes m·(n+1) memory cells, wherein n and m are natural numbers greater than zero. Each of the plurality of memory cells is connected to one of (n+1) bitlines and one of m wordlines. The memory array further includes n outputs configured for reading a content of the memory array. The memory array further includes n output switches, wherein an i-th output switch is configured for selectively connecting, in response to a switching signal, either an i-th bitline or an (i+1)-th bitline to an i-th output, and wherein i is a natural number and 0≦i≦n−1. The memory array further includes an (n+1)-th output switch, wherein the (n+1)-th output switch is configured for selectively connecting, in response to the switching signal, either the (n+1)-th bitline or a defined potential to an (n+1)-th output.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.