Combination interconnect structure and methods of forming same
US9716035B2 · kind B2 · utility
6Cited by
38References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2014 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | Nov 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment semiconductor device includes a substrate and a dielectric layer over the substrate. The dielectric layer includes a first conductive line and a second conductive line. The second conductive line comprises a different conductive material than the first conductive line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.