Interlayer dielectric structure with high aspect ratio process (HARP)
US9716044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2011 |
| Grant date | Jul 25, 2017 |
| Priority date | — |
| Expiry date | May 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0186
Abstract
The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.