Block storage protocol to RAM bypass
US9720604B2 · kind B2 · utility
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5References
21Claims
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Key dates
| Filing date | Aug 6, 2015 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Aug 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems are provided where a memory controller for non-volatile memory transfers data to and from random access memory over a second double data rate bus, and a host system access the random access memory over a first double data rate bus. The memory controller may transfer the data in response to a command received by the memory controller from a host system via a block storage protocol bus. Alternatively or in addition, the memory controller may transfer the data as part of caching data internal to the non-volatile memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.