Patent · US Active

Uncorrectable memory errors in pipelined CPUs

US9720764B2 · kind B2 · utility

1Cited by

4References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Michael Billeci · Poughkeepsie, US
Uwe Brandt · Eppelheim, DE
Christian Jacobi · West Park, US
Martin Recktenwald · Eppelheim, DE

Key dates

Filing date	Jul 30, 2015
Grant date	Aug 1, 2017
Priority date	—
Expiry date	Oct 1, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/1032
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Uncorrectable memory errors in pipelined central processing units. A processor core may be connected to a memory system and it may include a processor cache. In response to determining an uncorrectable error in data stored in the memory system, the address of a memory location of the uncorrectable error is stored in an address buffer and a recovery procedure is performed for the processor core. When fetching data from a memory location and if it is determined that the address of this memory location is stored in the address buffer, the content of a cache line related to the address is moved into a quarantine buffer of the processor core. When detecting an error in the data of the moved cache line, a repair procedure for the data of this address is triggered.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.