Patent · US Active

Architecture to improve write-ability in SRAM

US9721650B1 · kind B1 · utility

5Cited by

5References

16Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Pradeep Raj · Atrauli, IN
Sharad Gupta · New Delhi, IN
Rahul Sahu · Kanchinakote, IN
Lakshmikantha Holla Vakwadi · Bengaluru, IN

Key dates

Filing date	Sep 19, 2016
Grant date	Aug 1, 2017
Priority date	—
Expiry date	Sep 19, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG11C5/14
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory and apparatus are disclosed. The memory includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core. Additionally, the memory includes a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core. The apparatus includes at least one processor. The apparatus also includes a memory array. The memory array includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core and a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.