Semiconductor device and manufacturing method thereof
US9721894B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2016 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Nov 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.