Static random access memory (SRAM) cells including vertical channel transistors
US9721957B2 · kind B2 · utility
15Cited by
14References
13Claims
0Family size
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Key dates
| Filing date | Dec 8, 2014 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Jan 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/221
Abstract
A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.