Semiconductor memory device

US9721961B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Mutsumi Okajima · Somalomo, CM
• Atsushi OGA · Somalomo, CM
• Takeshi Yamaguchi · Sakai, JP
• Hiroyuki Ode · Kure, JP
• Toshiharu Tanaka · Tokyo, JP
• Natsuki Fukuda · Yokkaichi, JP

Key dates

• Filing date: Dec 15, 2015
• Grant date: Aug 1, 2017
• Expiry date: Dec 15, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/841

Abstract

In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.