Isolated gate field effect transistor and manufacture method thereof
US9722064B2 · kind B2 · utility
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13Claims
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Key dates
| Filing date | May 21, 2013 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | May 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An isolated gate field effect transistor and the manufacture method thereof. The isolated gate field effect transistor includes a substrate; a nitride transistor structure arranged on the substrate; a dielectric layer on the nitride transistor structure, where the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer and material of the second dielectric layer includes metal; a groove formed in a gate region and at least partially through the dielectric layer; a metal gate formed in the groove; and a source electrode and a drain electrode located at two ohmic contact regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.