Semiconductor device
US9722075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2014 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Oct 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
Described herein is a semiconductor device including a semiconductor substrate in which an element region and a termination region surrounding the element region are provided. The element region includes: a gate trench; a gate insulating film; and a gate electrode. The termination region includes: a plurality of termination trenches provided around the element region; an inner trench insulating layer located inside of each of the plurality of termination trenches; and an upper surface insulating layer located at an upper surface of the semiconductor substrate in the termination region. The upper surface insulating layer includes a first portion and a second portion having a thinner thickness than the first portion and located at a location separated from the element region than the first portion, and a gate wiring is located at an upper surface of the first portion and is not located at an upper surface of the second portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.