Patent · US Active

Testing method and testing system for semiconductor element

US9726713B2 · kind B2 · utility

1Cited by
6References
10Claims
0Family size

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Key dates

Filing dateApr 16, 2013
Grant dateAug 8, 2017
Priority date
Expiry dateAug 26, 2035

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/275
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A testing method and testing system for a semiconductor element are provided. The method includes following steps. A level of a testing electrostatic discharge (ESD) voltage is determined. A plurality of sample components is provided. The testing ESD voltage is imposed on the sample components for testing ESD decay rates of the sample components. ESD withstand voltages of the sample components are detected. The relation between the ESD withstand voltages and the electrostatic discharge rates are recorded to a database. The testing ESD voltage is imposed on the semiconductor element for testing an ESD decay rate of the semiconductor element. The database is looked up according to the ESD decay rate of the semiconductor element to determine an ESD withstand voltage of the semiconductor element.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.