Multi-level table deltas
US9727453B2 · kind B2 · utility
0Cited by
1References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Nov 3, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7207
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system or flash card may include an algorithm or process for managing the handling of large tables in memory. A delta may be used for each table to accumulate updates. There may be a plurality of deltas for a multi-level delta structure. In one example, the first level delta is stored in random access memory (RAM), while the other level deltas are stored in the flash memory. Multiple-level deltas may improve the number of flash writes and reduce the number and amount of each flush to the actual table in flash. The use of multi-level deltas may improve performance by more efficiently writing to the table in flash.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.