Method and apparatus for physical-aware hold violation fixing
US9727684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2015 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Nov 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method for fixing hold time violations in circuits. The method comprises: creating a topology diagram of the circuit with a branch indicating a signal path where the hold time violation occurs in the circuit, and a node on the branch indicating a port of an element where the hold time violation occurs; dividing the circuit into a plurality of regions; and placing a hold time correction element selectively in a region corresponding to the node in the topology diagram to fix the hold time violation thereof, according to a circuit element density of the region corresponding to the node in the topology diagram. With this method there will be no new element in a region whose circuit element density is excessively large, and it is unnecessary to move an element which has been placed in the circuit and an input/output pin thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.