System and method for automatic detection of power up for a dual-rail circuit
US9728232B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 27, 2016 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | May 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
When powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in the dual-rail memory circuit precisely controls an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.