Space-efficient underfilling techniques for electronic assemblies
US9728425B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2016 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Apr 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/92125
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Space-efficient underfilling techniques for electronic assemblies are described. According to some such techniques, an underfilling method may comprise mounting an electronic element on a surface of a substrate, dispensing an underfill material upon the surface of the substrate within a dispense region for forming an underfill for the electronic element, and projecting curing rays upon at least a portion of the dispensed underfill material to inhibit an outward flow of dispensed underfill material from the dispense region, and the underfill material may comprise a non-visible light (NVL)-curable material. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.