Cap chip and reroute layer for stacked microelectronic module
US9728507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2012 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Jul 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4647
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A cap chip or high density reroute layer for use in a stacked microelectronic module. A first set of electrically conductive reroute layers are defined on a sacrificial substrate. One or more stud bump columns are defined on an exposed conducive pad on a conductive reroute layer. One or more active or passive electronic elements, or both may be electrically coupled to one or more exposed conductive pads. The layer is encapsulated in an encapsulant and the stud bump columns exposed by removing a portion of the encapsulant. A second set of electrically conductive reroute layers is defined on the layer and electrically coupled to the stud bumps. The sacrificial substrate is removed to provide a cap chip or reroute layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.