Vertical memory blocks and related devices and methods
US9728548B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2015 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Nov 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a dielectric stack of alternating dielectric materials and at least one conductive via extending through the dielectric stack. Semiconductor devices including a vertical memory block include at least one vertical memory block, which includes slots extending between adjacent memory cells of a three-dimensional array. The slots are separated by a first distance in a first portion of the block, and by a second, greater distance in a second portion of the block. Methods of forming vertical memory blocks include forming slots separated by a first distance in a memory array region and by a second, greater distance in a via region. At least one conductive via is formed through a stack of alternating first and second dielectric materials in the via region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.