Metal-insulator-metal structure and method for forming the same
US9728597B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2015 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Jul 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5223
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a dielectric layer over the first passivation layer by a second atomic layer deposition process and forming a second passivation layer over the dielectric layer by a third atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the second passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.