Semiconductor devices having a spacer on an isolation region
US9728643B2 · kind B2 · utility
2Cited by
3References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 18, 2015 |
| Grant date | Aug 8, 2017 |
| Priority date | — |
| Expiry date | Dec 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A semiconductor device including a fin active region protruding from a substrate and an isolation region defining the fin active region, a gate pattern intersecting the fin active region and the isolation region, and gate spacer formed on a side surface of the gate pattern and extending onto a surface of the isolation region is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.