Super multiply add (super madd) instruction
US9733935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2011 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Feb 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.