Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads
US9734033B2 · kind B2 · utility
0Cited by
16References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2014 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Dec 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.