Electronic device and method for fabricating the same
US9734060B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2015 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Oct 1, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.