System and methods for caching a small size I/O to improve caching device endurance
US9734062B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2013 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Nov 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/122
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the cache-lines comprises a plurality of sub-cache lines. Each of the plurality of cache-lines and each of the plurality of sub-cache lines is associated with meta-data indicating one or more of a dirty state and an invalid state. The controller is connected to the memory and configured to (i) recognize sub-cache line boundaries and (ii) process the I/O requests in multiples of a size of said sub-cache lines to minimize cache-fills.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.