Method of determining galvanic corrosion and interconnect structure in a semiconductor device for prevention of galvanic corrosion
US9734271B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 10, 2015 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Dec 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, in a method for a semiconductor device having an interconnect structure, a design layout is received. A metal line in the design layout is identified, which has at least one via thereon and does not couple downward with an oxide diffusion region. The area of a gate oxide coupled with the metal line is obtained from the design layout. The method comprises determining whether the area of the gate oxide is greater than a first predetermined value. When the area of the gate oxide is greater than the first predetermined value, a charge release path is coupled with the metal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.