Caching of adaptively sized cache tiles in a unified L2 cache with surface compression
US9734548B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2013 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Aug 28, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention includes techniques for adaptively sizing cache tiles in a graphics system. A device driver associated with a graphics system sets a cache tile size associated with a cache tile to a first size. The detects a change from a first render target configuration that includes a first set of render targets to a second render target configuration that includes a second set of render targets. The device driver sets the cache tile size to a second size based on the second render target configuration. One advantage of the disclosed approach is that the cache tile size is adaptively sized, resulting in fewer cache tiles for less complex render target configurations. Adaptively sizing cache tiles leads to more efficient processor utilization and reduced power requirements. In addition, a unified L2 cache tile allows dynamic partitioning of cache memory between cache tile data and other data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.