Isolation between semiconductor components

US9735112B2 · kind B2 · utility

Assignee

• FAIRCHILD SEMICONDUCTOR CORPORATION · US

Inventors

• John Constantino · Livermore, US
• Timwah Luk · Scarborough, US
• Ahmad Ashrafzadeh · معلمی نژاد, US
• Robert L. Krause · San Jose, US
• Etan Shacham · Cupertino, US
• Maria Clemens Y. Quinones · Tagbao, PH
• Janusz Bryzek · Oakland, US
• Chung-Lin Wu · Hsinchu, TW

Key dates

• Filing date: Jan 9, 2015
• Grant date: Aug 15, 2017
• Expiry date: Jan 9, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19105
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.