Chip packages and methods of manufacture thereof
US9735130B2 · kind B2 · utility
3Cited by
6References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2014 |
| Grant date | Aug 15, 2017 |
| Priority date | — |
| Expiry date | Aug 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package may include: a first die; at least one second die disposed over the first die; and a lid disposed over lateral portions of the first die and at least partially surrounding the at least one second die, the lid having inclined sidewalls spaced apart from and facing the at least one second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.