Multi-granular cache management in multi-processor computing environments
US9740616B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2015 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Dec 9, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Each cache is associated with a directory having a number of directory entries and with a side table having a smaller number of entries. The directory entry for a cache line associates the cache line with a tag and a set of full-line descriptive bits. Creating a side table entry for the cache line places the cache line in sub-line coherency mode. The side table entry associates each of the sub-cache line portions of the cache line with a set of sub-line descriptive bits. Removing the side table entry may return the cache line to full-line coherency mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.