Method to measure edge-rate timing penalty of digital integrated circuits
US9740807B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2015 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Aug 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models are described. Unbalanced circuit elements have large edge-rates at their input and small edge-rates at their output. Unbalanced circuit elements may be analyzed using a modified loaded ring oscillator. A statistical model and a fixed-corner model may be used to calculate timing delays associated with the unbalanced circuit elements and a timing delay error between the two models. The timing delay error may then be used to correct timing delays computed by static-timing models for similar unbalanced circuit elements within a more complex digital circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.