Virtual cell model geometry compression
US9740812B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2015 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Mar 30, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor designs are large and complex, typically consisting of numerous circuits called cells. To handle complexity, hierarchical structures are imposed on the semiconductor design to help accomplish analysis, simulation, verification, and so on. The hierarchical structures define architecture, behavior, function, structure, etc. of the semiconductor design. Virtual cells are constructed to compress cell geometries and ease the various design tasks. A cell and multiple instances of the cell are identified within the semiconductor design and the virtual hierarchical levels describing the design. Virtual hierarchical layer (VHL) data based on the cell is loaded. A virtual cell model representative of the cell is obtained. Interactions between cell data and VHL data are determined, and relevant portions of shapes are selected. Data within the virtual cell model is reduced based on the determined interactions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.