Semiconductor memory device and method of operating the same
US9741454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2016 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Jul 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.