Methods for manufacturing a spacer with desired profile in an advanced patterning process
US9741566B2 · kind B2 · utility
1Cited by
1References
18Claims
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Key dates
| Filing date | Feb 12, 2016 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Feb 12, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments herein provide apparatus and methods for performing an etching process on a spacer layer with good profile control in multiple patterning processes. In one embodiment, a method for patterning a spacer layer during a multiple patterning process includes conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has having a first group of openings defined therebetween and etching the spacer layer disposed on the substrate while forming an oxidation layer on the spacer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.