SRAM well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array
US9741724B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2015 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Oct 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.