Integrated circuit devices including source/drain extension regions and methods of forming the same
US9741811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2015 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Dec 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Integrated circuit devices may include a stack that includes channel regions and gate electrodes stacked in an alternating sequence in a vertical direction. The channel regions may include impurities having a first conductivity type. The integrated circuit devices may also include source/drain regions on respective opposing sides of the stack, and the source/drain regions may be spaced apart from each other in a horizontal direction and may include impurities having a second conductivity type that is different from the first conductivity type. The integrated circuit devices may further include extension regions that may be between respective ones of channel regions and one of the source/drain regions and may include impurities having the second conductivity type. Each of the extension regions may have a thickness in the vertical direction that is less than those of the channel regions and the one of the source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.