Patent · US Active

Amorphous silicon semiconductor TFT backboard structure

US9741858B2 · kind B2 · utility

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4References
12Claims
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Key dates

Filing dateOct 13, 2015
Grant dateAug 22, 2017
Priority date
Expiry dateMar 1, 2036

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D30/6746

Abstract

The present invention provides an amorphous silicon semiconductor TFT backboard structure, which includes a semiconductor layer (4) that has a multi-layer structure including a bottom amorphous silicon layer (41) in contact with a gate insulation layer (3), an N-type heavily-doped amorphous silicon layer (42) in contact with a source electrode (6) and a drain electrode (7), at least two N-type lightly-doped amorphous silicon layers (43) sandwiched between the bottom amorphous silicon layer (41) and the N-type heavily-doped amorphous silicon layer (42), a first intermediate amorphous silicon layer (44) separating every two adjacent ones of the lightly-doped amorphous silicon layers (43), and a second intermediate amorphous silicon layer (45) separating the N-type heavily-doped amorphous silicon layer (42) from the one of the lightly-doped amorphous silicon layers (43) that is closest to the N-type heavily-doped amorphous silicon layer (42). Such a structure further reduces the energy barrier between the drain electrode and the semiconductor layer, making injection of electron easier and ensuring the ON-state current is not lowered down and also helping increase the barrier for trans…

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.