Buffer circuit robust to variation of reference voltage signal
US9742355B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2015 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Dec 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45702
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.