Patent · US Active

Phase-locked loop having sampling phase detector

US9742380B1 · kind B1 · utility

10Cited by

1References

20Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Mayank Raj · San Jose, US
Parag Upadhyaya · Los Gatos, US
Adebabay M. Bekele · San Jose, US

Key dates

Filing date	Jun 1, 2016
Grant date	Aug 22, 2017
Priority date	—
Expiry date	Jun 1, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/1974
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An example a phase-locked loop (PLL) circuit includes a sampling phase detector configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter configured to filter the second control current and generate an oscillator control voltage. The PLL further includes a voltage controlled oscillator (VCO) configured to generate an output clock based on the oscillator control voltage. The PLL further includes a frequency divider configured to generate the reference clock from the output clock.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.