Floating point unit with support for variable length numbers
US9747073B2 · kind B2 · utility
3Cited by
7References
3Claims
0Family size
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Key dates
| Filing date | Mar 6, 2014 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Feb 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4912
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.