Error monitoring of a memory device containing embedded error correction
US9747148B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2017 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Jan 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.