Computer processor employing split crossbar circuit for operand routing and slot-based organization of functional units
US9747238B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2014 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Oct 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer processor including a plurality of functional units that performs operations that produce result operands at different characteristic latencies over multiple cycles. An interconnect network provides data paths for transfer of operand data between functional units. The interconnect network includes first and second crossbar parts. The first crossbar part is configured to route result operands produced with the lowest characteristic latency to any other functional unit. The second crossbar part is configured to route result operands with higher characteristic latency relative to the lowest characteristic latency to the first crossbar part where such result operands are in turn routed to any functional unit. In another aspect, the functional units can be organized as multiple slots where each slot can produce multiple result operands of different characteristic latencies in the same cycle, and wherein each slot employs separate result registers for each characteristic latency present on the slot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.